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GS8182S18D-267/250/200/167
165-Bump BGA Commercial Temp Industrial Temp Features
* Simultaneous Read and Write SigmaQuadTM Interface * JEDEC-standard pinout and package * Dual Double Data Rate interface * Byte Write controls sampled at data-in time * DLL circuitry for wide output data valid window and future frequency scaling * Burst of 2 Read and Write * 1.8 V +150/-100 mV core power supply * 1.5 V or 1.8 V HSTL Interface * Pipelined read operation * Fully coherent read and write pipelines * ZQ mode pin for programmable output drive strength * IEEE 1149.1 JTAG-compliant Boundary Scan * 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package * RoHS-compliant 165-bump BGA package available * Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
18Mb Burst of 2 DDR SigmaSIO-II SRAM
267 MHz-167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O
Bottom View
165-Bump, 13 mm x 15 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1 routed internally to fire the output registers instead. Each Burst of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs, CQ and CQ, which are synchronized with read data output. When used in a source synchronous clocking scheme, the Echo Clock outputs can be used to fire input registers at the data's destination. Because Separate I/O Burst of 2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a Burst of 2 RAM is always one address pin less than the advertised index depth (e.g., the 1M x 18 has a 512K addressable index).
SigmaRAMTM Family Overview
GS8182S18 are built in compliance with the SigmaSIO-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. If the C clocks are tied high, the K clocks are
Parameter Synopsis
-267 tKHKH tKHQV 3.75 ns 0.45 ns -250 4.0 ns 0.45 ns -200 5.0 ns 0.45 ns -167 6.0 ns 0.5 ns
Rev: 1.08a 8/2005
1/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
1M x 18 SigmaQuad SRAM--Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS/SA (144Mb) Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 NC/SA (36Mb) D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 VSS/SA (72Mb) NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
11 x 15 Bump BGA--13 x 15 mm2 Body--1 mm Bump Pitch Notes: 1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb 2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 3. It is recommended that H1 be tied low for compatibility with future devices.
Rev: 1.08a 8/2005
2/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Pin Description Table Symbol
SA NC R/W BW0-BW1 K C TMS TDI TCK TDO VREF ZQ K C DOFF LD CQ CQ D Q VDD VDDQ VSS
Description
Synchronous Address Inputs No Connect Synchronous Read/Write Synchronous Byte Writes Input Clock Output Clock Test Mode Select Test Data Input Test Clock Input Test Data Output HSTL Input Reference Voltage Output Impedance Matching Input Input Clock Output Clock DLL Disable Synchronous Load Pin Output Echo Clock Output Echo Clock Synchronous Data Inputs Synchronous Data Outputs Power Supply Isolated Output Buffer Supply Power Supply: Ground
Type
Input -- Input Input Input Input Input Input Input Output Input Input Input Output -- -- Output Output Input Output Supply Supply Supply
Comments
-- -- Active Low Active High Active High -- -- -- -- -- -- Active Low Active Low Active Low Active Low Active Low Active High
1.8 V Nominal 1.8 or 1.5 V Nominal --
Notes: 1. C, C, K, or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD, output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. NC = Not Connected to die or any other pin
Background
Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write addresses like SigmaCIO SRAMs, but in a separate I/O configuration. Rev: 1.08a 8/2005 3/31 (c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Like a SigmaQuad SRAM, a SigmaSIO-II SRAM can execute an alternating sequence of reads and writes. However, doing so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would keep both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device. SigmaCIO SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic between two electrically independent busses is desired. Each of the three SigmaQuad Family SRAMs--SigmaQuad, SigmaCIO, and SigmaSIO--supports similar address rates because random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how the RAM's interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at hand. Burst of 2 SigmaSIO-II SRAM DDR Read The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on the R/W pin begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high).
SigmaSIO-II Double Data Rate SRAM Read First
Read A Write B Read C Write D NOP Read E Read F NOP
K K Address LD R/W BWx D C C Q CQ CQ A A+1 C C+1 E E+1 F B B B+1 B+1 D D D+1 D+1 A B C D E F
Rev: 1.08a 8/2005
4/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Burst of 2 SigmaSIO-II SRAM DDR Write The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.
SigmaSIO-II Double Data Rate SRAM Write First
Write A Read B NOP Read C Write D NOP Read E Read F NOP
K K Address LD R/W BWx D C C Q CQ CQ B B+1 C C+1 E E+1 F A A A+1 A+1 D D D+1 D+1 A B C D E F
Rev: 1.08a 8/2005
5/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Special Functions
Byte Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0-D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.
Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time
Beat 1 Beat 2
BW0
0 1
BW1
1 0
D0-D8
Data In Don't Care
D9-D17
Don't Care Data In
Resulting Write Operation Beat 1 D0-D8
Written
Beat 2 D0-D8
Unchanged
D9-D17
Unchanged
D9-D17
Written
Output Register Control SigmaSIO-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs.
Rev: 1.08a 8/2005
6/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Example Four Bank Depth Expansion Schematic
R3 W3 R2 W2 R1 W1 R0 W0 A0-An K D1-Dn Bank 0 A W R K D C C Q1-Qn CQ0 CQ1 CQ2 CQ3 CQ Q Bank 1 A W R K D C CQ Q Bank 2 A W R K D C CQ Q Bank 3 A W R K D C CQ Q
Note: For simplicity BWn is not shown.
Rev: 1.08a 8/2005
7/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Burst of 2 SigmaSIO-II SRAM Depth Expansion
Write A Read B Write C Read D Write E Read F Read G Read H NOP
K K Address LD(Bank_1) LD(Bank_2) R/W(Bank_1) R/W(Bank_2) BWx(Bank_1) BWx(Bank_2) D(Bank_1) D(Bank_2) C(Bank_1) C(Bank_1) Q(Bank_1) CQ(Bank)1 CQ(Bank_1) C(Bank_2) C(Bank_2) Q(Bank_2) CQ(Bank_2) CQ(Bank_2) B B+1 F F+1 D D+1 G A A+1 C C+1 A A+1 C C+1 E E+1 E E+1 A B C D E F G H
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 150 and 300. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM's output impedance circuitry compensates for drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps.
Rev: 1.08a 8/2005
8/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Separate I/O Burst of 2 SigmaSIO-II SRAM Truth Table A K (tn)
X V V
LD K (tn)
1 0 0
R/W K (tn)
X 1 0
Current Operation K (tn)
Deselect Read Write
D K (tn+1)
X X D0
D K (tn+1)
-- -- D1
Q K (tn+1)
Hi-Z Q0 Hi-Z
Q K (tn+1)
-- Q1 --
Notes: 1. "1" = input "high"; "0" = input "low"; "V" = input "valid"; "X" = input "don't care" 2. "--" indicates that the input requirement or output state is determined by the next operation. 3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations. 4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations. 5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when preceded by a Read command. 6. CQ is never tristated. 7. Users should not clock in metastable addresses.
Rev: 1.08a 8/2005
9/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
x18 Byte Write Clock Truth Table BW K (tn+1)
T T F F
BW K (tn+2)
T F T F
Current Operation K (tn)
Write Dx stored if BWn = 0 in both data transfers Write Dx stored if BWn = 0 in 1st data transfer only Write Dx stored if BWn = 0 in 2nd data transfer only Write Abort No Dx stored in either data transfer
D K (tn+1)
D1 D1 X X
D K (tn+2)
D2 X D2 X
Notes: 1. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false". 2. If one or more BWn = 0, then BW = "T", else BW = "F".
x18 Byte Write Enable (BWn) Truth Table BW1 BW0
1 0 1 0 1 1 0 0
D9-D17
Don't Care Don't Care Data In Data In
D0-D8
Don't Care Data In Don't Care Data In
Rev: 1.08a 8/2005
10/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
State Diagram
Power-Up
LOAD
NOP
LOAD
LOAD
Load New Address LOAD LOAD READ WRITE LOAD
DDR Read
DDR Write
Rev: 1.08a 8/2005
11/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VREF VI/O VIN IIN IOUT TJ TSTG TSUB
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage in VREF Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Maximum Junction Temperature Storage Temperature Storage Under Bias
Value
-0.5 to 2.9 -0.5 to VDD -0.5 to VDDQ -0.5 to VDDQ +0.3 ( 2.9 V max.) -0.5 to VDDQ +0.3 ( 2.9 V max.) +/-100 +/-100 125 -55 to 125 -50 to 100
Unit
V V V V V mA dc mA dc
oC o o
C C
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions Power Supplies Parameter
Supply Voltage 1.5 V I/O Supply Voltage 1.8 V I/O Supply Voltage Reference Voltage
Symbol
VDD VDDQ VDDQ VREF
Min.
1.7 1.4 1.7 0.68
Typ.
1.8 1.5 1.8 --
Max.
1.95 1.65 1.95 0.95
Unit
V V V V
Notes
1 1 1
Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V VDDQ 1.6 V (i.e., 1.5 V I/O) and 1.7 V VDDQ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case. 2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD.
Operating Temperature Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
TA TA
Min.
0 -40
Typ.
25 25
Max.
70 85
Unit
C C
Notes
2 2
Rev: 1.08a 8/2005
12/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
HSTL I/O DC Input Characteristics Parameter
DC Input Logic High DC Input Logic Low Note: Compatible with both 1.8 V and 1.5 V I/O drivers
Symbol
VIH (dc) VIL (dc)
Min
VREF + 0.1 -0.3
Max
VDDQ + 0.3 VREF - 0.1
Units
mV mV
Notes
1 1
HSTL I/O AC Input Characteristics Parameter
AC Input Logic High AC Input Logic Low VREF Peak to Peak AC Voltage
Symbol
VIH (ac) VIL (ac) VREF (ac)
Min
VREF + 0.2 -- --
Max
-- VREF - 0.2 5% VREF (DC)
Units
mV mV mV
Notes
3,4 3,4 1
Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers. 4. See AC Input Definition drawing below.
HSTL I/O AC Input Definitions
VIH (ac) VREF VIL (ac)
Undershoot Measurement and Timing
VIH
Overshoot Measurement and Timing
20% tKHKH VDD + 1.0 V
VSS 50% VSS - 1.0 V 20% tKHKH
50% VDD
VIL
Rev: 1.08a 8/2005
13/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance Output Capacitance Note: This parameter is sample tested.
Symbol
CIN COUT
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6
Max.
5 7
Unit
pF pF
AC Test Conditions Parameter
Input high level Input low level Max. input slew rate Input reference level Output reference level Note: Test conditions as specified with output loading as shown unless otherwise noted.
Conditions
VDDQ 0V 2 V/ns VDDQ/2 VDDQ/2
AC Test Load Diagram
DQ 50 VT = VDDQ/2 RQ = 250 (HSTL I/O) VREF = 0.75 V
Input and Output Leakage Characteristics Parameter
Input Leakage Current (except mode pins) Output Leakage Current
Symbol
IIL IOL
Test Conditions
VIN = 0 to VDD Output Disable, VOUT = 0 to VDDQ
Min.
-2 uA -2 uA
Max
2 uA 2 uA
Notes
Rev: 1.08a 8/2005
14/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter
Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage
Symbol
VOH1 VOL1 VOH2 VOL2
Min.
VDDQ/2 - 0.12 VDDQ/2 - 0.12 VDDQ - 0.2 Vss
Max.
VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2
Units
V V V V
Notes
1, 3 2, 3 4, 5 4, 6
Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/- 15% @ VOH = VDDQ/2 (for: 175 RQ 350). 2. IOL = (VDDQ/2) / (RQ/5) +/- 15% @ VOL = VDDQ/2 (for: 175 RQ 350). 3. Parameter tested with RQ = 250 and VDDQ = 1.5 V or 1.8 V 4. Minimum Impedance mode, ZQ = VSS 5. IOH = -1.0 mA 6. IOL = 1.0 mA
Operating Currents
-267 Parameter Org Symbol 0C to 70C
475 mA
-250 0C to 70C
450 mA
-200 0C to 70C
400 mA
-167 0C to 70C
350 mA
-40C to +85C
485 mA
-40C to +85C
460 mA
-40C to +85C
410 mA
-40C to +85C
360 mA
Test Conditions
Operating Current Standby Current (NOP)
x18
IDD
VDD =max.; IOUT = 0 mA; Cycle Time tKHKH min. Device deselected; IOUT = 0 mA; f = max; All inputs 0.2 V or VDD - 0.2 V
x18
ISB1
230 mA
235 mA
220 mA
225 mA
205 mA
210 mA
195 mA
200 mA
Notes: 1. Power measured with output pins floating. 2. All inputs (except ZQ, VREF) are held at either VIH or VIL. 3. Operating supply currents are measured at 100% buss utilization. 4. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.
Rev: 1.08a 8/2005
15/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
AC Electrical Characteristics
Parameter
K Clock Cycle Time C Clock Cycle Time K Clock High Pulse Width C Clock High Pulse Width K Clock Low Pulse Width C Clock Low Pulse Width Clock to Clock Delay Address Input Setup Time Address Input Hold Time Control Input Setup Time Control Input Hold Time Data and Byte Write Input Setup Time Data and Byte Write Input Hold Time K Clock High to Data Output Valid C Clock High to Data Output Valid K Clock High to Data Output Hold C Clock High to Data Output Hold K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z K Clock High to Data Output High-Z C Clock High to Data Output High-Z K Clock High to CQ Clock High C Clock High to CQ Clock High K Clock High to CQ Clock Hold C Clock High to CQ Clock Hold CQ Clock High to Data Output Valid CQ Clock High to Data Output Hold
Symbol
tKHKH tCHCH tKHKL tCHCL tKLKH tCLCH tKHKH tCHCH tAVKH tKHAX tBVKH tKHBX tDVKH tKHDX tKHQV tCHQV tKHQX tCHQX tKHQX1 tCHQX1 tKHQZ tCHQZ tKHCQV tCHCQV tKHCQX tCHCQX tCQHQV tCQHQX
-267
Min 3.75 1.6 1.6 1.8 0.5 0.5 0.5 0.5 0.35 0.35 -- -0.45 -0.45 -- -- -0.45 -- -0.3 Max 6.3 -- -- -- -- -- -- -- -- -- 0.45 -- -- 0.45 0.45 -- 0.3 -- Min 4.0 1.6 1.6 1.8 0.5 0.5 0.5 0.5 0.35 0.35 --
-250
Max 6.3 -- -- -- -- -- -- -- -- -- 0.45 -- -- 0.45 0.45 -- 0.3 -- Min 5.0 2.0 2.0 2.3 0.6 0.6 0.6 0.6 0.4 0.4 --
-200
Max 7.88 -- -- -- -- -- -- -- -- -- 0.45 -- -- 0.45 0.45 -- 0.35 -- Min 6.0 2.4 2.4 2.8 0.7 0.7 0.7 0.7 0.5 0.5 -- -0.5 -0.5 -- -- -0.5 -- -0.4
-167
Max 8.4 -- -- -- -- -- -- -- -- -- 0.5 -- -- 0.5 0.5 -- 0.4 --
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
1 1
-0.45 -0.45 -- -- -0.45 -- -0.3
-0.45 -0.45 -- -- -0.45 -- -0.35
2 2,3 2,3
2 2 2
Notes: 1. These parameters apply to control inputs R and W. 2. These parameters are guaranteed by design through extensive corner lot characterization. 3. These parameters are measured at 50 mV from steady state voltage.
Rev: 1.08a 8/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
K Controlled Read-First Timing Diagram
Read A KHKL KHKH K KH#KH K AVKH KHAX Address A IVKH LD IVKH R/W IVKH KHIX BWx B DVKH KHDX D KHQX1 Q CQ KHCQV KHCQX CQ CQHQV CQHQX A A+1 B B+1 KHQZ C KHQV C+1 D KHQX D+1 B+1 KHIX B KHIX C D E KLKH Write B Read C Read E Deselect Deselect
Rev: 1.08a 8/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
K Controlled Write-First Timing Diagram
NOP Write A Read B KHKL KHKH K KH#KH K AVKH KHAX Address IVKH LD IVKH R/W KHIX IVKH BWx A A+1 KHDX DVKH D A A+1 D D+1 KHQV KHQX1 Q KHCQX KHCQV CQ KHCQX KHCQV CQ CQHQV CQHQX B B+1 KHQX C C+1 KHQZ E E+1 D D+1 E E+1 KHIX A KHIX B C D E KLKH Read C Write D Write E Deselect
Rev: 1.08a 8/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
C Controlled Read-First Timing Diagram
Read A KHKL KHKH K KHKH# K AVKH KHAX Address A IVKH KHIX LD IVKH KHIX R/W KHIX IVKH BWx B B+1 KHDX DVKH D CLCH KHCH C CHCH# C CHQX1 Q CQ CHCQX CHCQV CQ CQHCV CQHQX A A+1 CHQZ C CHQV C+1 CHQX D D+1 CHCL CHCH B B+1 B C D KLKH Write B Read C Read D Deselect Deselect
Rev: 1.08a 8/2005
19/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
C Controlled Write-First Timing Diagram
NOP Write A Read B KHKL KHKH K KH#KH K KHAX AVKH Addr IVKH LD IVKH R/W KHIX IVKH BWx A A+1 KHDX DVKH D A A+1 KHKL KHKH C KH#KH C CHQX1 CHQX CHQV Q CQ CQHQV CQ CQHQX B B+1 CHQZ KLKH C C+1 D D+1 C C+1 D D+1 KHIX A KHIX B C D E KLKH Write C Write D Read E Deselect
Rev: 1.08a 8/2005
20/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
JTAG Port Operation
Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Port Registers JTAG Pin Descriptions Pin
TCK
Pin Name
Test Clock
I/O
In
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.
TMS
Test Mode Select
In
TDI
Test Data In
In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.08a 8/2005
21/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
* * *
108
*
*
*
*
*
*
* *
1
Boundary Scan Register
0
Bypass Register
210
0
Instruction Register TDI ID Code Register
31 30 29
TDO
*
***
210
Control Signals TMS TCK Test Access Port (TAP) Controller
Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Contents TBD for this part.
Rev: 1.08a 8/2005
22/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Tap Controller Instruction Set ID Register Contents
Die Revision Code GSI Technology JEDEC Vendor ID Code Presence Register 0 1
Not Used
I/O Configuration
Bit # x18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X 0 0 0 X 1 0 0 0 1 0 0 0 1 0 1 0 0 0 011011001
Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
Rev: 1.08a 8/2005
23/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
JTAG Tap Controller State Diagram
1
Test Logic Reset
0 1 1 1
0
Run Test Idle
Select DR
0 1
Select IR
0 1
Capture DR
0
Capture IR
0
Shift DR
1 1
0 1
Shift IR
1
0
Exit1 DR
0
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR
1
0
Exit2 IR
1
0
Update DR
1 0
Update IR
1 0
Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins.
Rev: 1.08a 8/2005
24/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.08a 8/2005
25/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
JTAG Port AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level
Conditions
VDD - 0.2 V 0.2 V 1 V/ns VDDQ/2 VDDQ/2 DQ
JTAG Port AC Test Load
50 VDDQ/2
* Distributed Test Jig Capacitance
30pF*
Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted.
JTAG TAP Instruction Set Summary Instruction
EXTEST IDCODE SAMPLE-Z
Code
000 001 010
Description
Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Places Bypass Register between TDI and TDO.
Notes
1 1, 2 1
RFU SAMPLE/ PRELOAD GSI RFU BYPASS
011 100 101 110 111
1 1 1 1 1
Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.08a 8/2005
26/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
JTAG Port Recommended Operating Conditions and DC Characteristics Parameter
Test Port Input High Voltage Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low
Symbol
VIHJ VILJ IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
0.6 * VDD -0.3 -300 -1 -1 1.7 -- VDDQ - 100 mV --
Max.
VDD2 +0.3 0.3 * VDD 1 100 1 -- 0.4 -- 100 mV
Unit Notes
V V uA uA uA V V V V 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9
Notes: 1. Input Under/overshoot voltage must be -1 V < Vi < VDD + 1V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = -4 mA 7. IOLJ = + 4 mA 8. IOHJC = -100 uA 9. IOHJC = +100 uA
JTAG Port Timing Diagram
tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input
tTKH
tTKL
Rev: 1.08a 8/2005
27/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
JTAG Port AC Electrical Characteristics
Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 -- 20 20 10 10 Max -- 20 -- -- -- -- Unit ns ns ns ns ns ns
Rev: 1.08a 8/2005
28/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167 Package Dimensions--165-Bump FPBGA (Package D; Variation 3)
A1 CORNER TOP VIEW BOTTOM VIEW O0.10 M C O0.25 M C A B O0.44~0.64 (165x) A1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
1.0 10.0 1.0
150.05
14.0
A
0.53 REF 0.35 C
1.0
1.0
0.20 C
B 0.20(4x)
130.05
Rev: 1.08a 8/2005
0.36~0.46 1.40 MAX.
0.36 REF
C
SEATING PLANE
29/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
Ordering Information--GSI SigmaSIO-II SRAM Org
1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18
Part Number1
GS8182S18D-267 GS8182S18D-250 GS8182S18D-200 GS8182S18D-167 GS8182S18D-267I GS8182S18D-250I GS8182S18D-200I GS8182S18D-167I GS8182S18GD-267 GS8182S18GD-250 GS8182S18GD-200 GS8182S18GD-167 GS8182S18GD-267I GS8182S18GD-250I GS8182S18GD-200I GS8182S18GD-167I
Type
SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM
Package
1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) RoHS-compliant 1 mm Pitch, 165-Pin BGA (var. 3) RoHS-compliant 1 mm Pitch, 165-Pin BGA (var. 3) RoHS-compliant 1 mm Pitch, 165-Pin BGA (var. 3) RoHS-compliant 1 mm Pitch, 165-Pin BGA (var. 3) RoHS-compliant 1 mm Pitch, 165-Pin BGA (var. 3) RoHS-compliant 1 mm Pitch, 165-Pin BGA (var. 3) RoHS-compliant 1 mm Pitch, 165-Pin BGA (var. 3) RoHS-compliant 1 mm Pitch, 165-Pin BGA (var. 3)
Speed (MHz)
267 250 200 167 267 250 200 167 267 250 200 167 267 250 200 167
TA3
C C C C I I I I C C C C I I I I
Status
MP MP MP MP MP MP MP MP PQ PQ PQ PQ PQ PQ PQ PQ
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8182S18D-250T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 3. MP = Mass Production. PQ = Pre-Qualification.
Rev: 1.08a 8/2005
30/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8182S18D-267/250/200/167
SigmaSIO-II Revision History File Name
8182Sxx_r1 8182Sxx_r1; 8182Sxx_r1_01 8182Sxx_r1_01; 8182Sxx_r1_02 8182Sxx_r1_02; 8182Sxx_r1_03 8182Sxx_r1_03; 8182Sxx_r1_04 Content Content Content Content
Format/Content
Description of changes
Creation of datasheet * Changed 330 MHz to 333MHz * Removed any references to 133 MHz or 100 MHz * Updated AC spec information * Comprehensive rewrite, including (but not limited to) tables, pinouts, and timing diagrams * Removed x36 configuration * Removed 333 and 300 MHz speed bins * Updated format * Updated timing diagrams * Corrected erroneous VDD information in pin description table * Deleted erroneous sentent in FLXDrive section * Added 165 BGA Pb-Free information * Added Storage Under Bias information * Incorporated IDD information into Operating Currents table * Updated Test Conditions for Operating Currents table * Added max numbers for tKHKH and tCHCH in AC Char. table * Added Clock to /Clock Delay timing to AC Char. table * Updated timing diagrams * Added 267 MHz speed bin
8182Sxx_r1_04; 8182Sxx_r1_05
Content
8182Sxx_r1_05; 8182Sxx_r1_06
Content
8182Sxx_r1_06; 8182Sxx_r1_07 8182Sxx_r1_07; 8182Sxx_r1_08
Content Content
Rev: 1.08a 8/2005
31/31
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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